---------------------------------------------------------------------------------
  -- Design Name : ID / EX+MEM Registers
  -- File Name   : R_Id_ExMem.vhd
  -- Function    : ID / EX+MEM Registers
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity R_Id_ExMem is
  port (
    clk         : in  std_logic;
    reset       : in  std_logic;
    stall       : in  std_logic;
    wrkIn       : in  std_logic;
    wrkOut      : out std_logic;
    idleIn      : in  std_logic;
    idleOut     : out std_logic;
    newAddrIn   : in  word32;
    newAddrOut  : out word32;
    rs1DataIn   : in  word32;
    rs1DataOut  : out word32;
    rs2DataIn   : in  word32;
    rs2DataOut  : out word32;
    opIn        : in  opCode;
    opOut       : out opCode;
    rdAddrIn    : in  RegAddr;
    rdAddrOut   : out RegAddr;      
    r1AddrIn    : in  RegAddr;
    r1AddrOut   : out RegAddr;
    r2AddrIn    : in  RegAddr;
    r2AddrOut   : out RegAddr
  );
end R_Id_ExMem;

architecture behavioral of R_Id_ExMem is
  signal instIn         : word32;
  signal instOut        : word32;
  signal zero           : std_logic_vector(LEN_WORD -1 downto 23);
  signal ld             : std_logic;
  signal workSignal     : std_logic;
  signal operation      : opCode;
begin  
  
  zero         <= (others => '0');
  instIn       <= zero & wrkIn & idleIn & r2AddrIn & r1AddrIn & rdAddrIn & opIn when reset = '0' else
                  (5 downto 0 => '1', others => '0'); --zeros & OPC_NOP;
  
  opOut        <= instOut( 5 downto 0);
  rdAddrOut    <= instOut(10 downto  6);
  r1AddrOut    <= instOut(15 downto 11);
  r2AddrOut    <= instOut(20 downto 16);
  idleOut      <= instOut(21);
  workSignal   <= instOut(22);
  wrkOut       <= workSignal;
  
  ld <= '1';
  
  inst: GenReg32 port map (
    clk    => clk,
    ld     => ld or reset,
    cl     => '0',
    regIn  => instIn,
    regOut => instOut
  );
  
  newAddr: GenReg32 port map (
    clk    => clk,
    ld     => ld,
    cl     => reset,
    regIn  => newAddrIn,
    regOut => newAddrOut
  );
  
  rs1Data: GenReg32 port map (
    clk    => clk,
    ld     => ld,
    cl     => reset,
    regIn  => rs1DataIn,
    regOut => rs1DataOut
  );
  
  rs2Data: GenReg32 port map (
    clk    => clk,
    ld     => ld,
    cl     => reset,
    regIn  => rs2DataIn,
    regOut => rs2DataOut
  );
  
end architecture behavioral;